As the massive volumes of electronically stored and transmitted data (e.g., “big data”) continue to increase, so does the need for electronic data storage that is reliable and cost effective, yet quickly accessible (e.g., low latency). Specifically, more computing applications are requiring that increasingly larger data sets be stored in “hot” locations for high speed access. Certain non-volatile memory (NVM) storage technologies, such as magnetic hard disk drives (HDDs), can provide a reliable, low cost storage solution, yet with relatively high access latencies. Such storage technologies might be used for large volumes of data in “cold” locations that are not often accessed (e.g., data warehouses, archives, etc.). Other volatile or “dynamic” memory storage technologies, such as dynamic random access memory (DRAM), provide lower access latencies, and might be used in “hot” locations near a computing host (e.g., CPU) to offer fast access to certain data for processing. Yet, such storage technologies can have a relatively high cost and risk of data loss (e.g., on power loss). Solid state NVM, such as Flash memory, can offer an improved form factor and access latency as compared to an HDD, yet still not approach the access latency of DRAM.
In some cases, DRAM and Flash can be combined in a hybrid memory module to deliver the fast data access of the DRAM and the non-volatile data integrity (e.g., data retention) enabled by the Flash memory. One such implementation is the non-volatile dual in-line memory module (NVDIMM), which stores data in DRAM for normal operation, and stores data in Flash for backup and/or restore operations (e.g., responsive to a power loss, system crash, normal system shutdown, etc.). Specifically, for example, the JEDEC standards organization has defined the NVDIMM-N product for such backup and/or restore applications. Many NVDIMM implementations can further be registered DIMMs (RDIMMs), which can use hardware registers and other logic, such as included in a registering clock driver (RDC), to buffer the address and control signals to the DRAM devices in order to expand the capacity of the memory channels. Other NVDIMM implementations can be load-reduced DIMMs (LRDIMMs), which can include data buffers to buffer the data signals in order to reduce the loading on the data bus and expand the capacity of the memory channels.
Unfortunately, legacy hybrid memory module architectures can have functional and performance limitations. Specifically, certain NVDIMM designs use the non-volatile memory controller (NVC) communications interface for DRAM read and write commands during data backup and data restore operations. In some cases, the phase relationship between the data transmitted to the DRAM from the NVC (e.g., during data restore) and the data clock provided by the RDC might be unknown. For example, various asynchronous delays (e.g., propagation delays, gate delays, buffer delays, printed circuit board trace delays, etc.) and/or synchronous delays (e.g., deterministic delays, logic stage delays, flip-flop delays, etc.) might be present in the NVDIMM. Such timing uncertainties can limit the performance and/or reliability of the hybrid memory module. Some legacy hybrid memory modules are further limited in the frequency of the data clock from the RDC as compared to the operating clock (e.g., local clock) of the NVC. Specifically, some designs can produce a data clock having a fixed divide-by-four relationship with the local clock. Such fixed ratios can limit the performance of the hybrid memory module at least as pertains to burst control flexibility, power management flexibility, maximum data clock frequency, restore latencies, NVC to RCD communication latencies, and other performance characteristics. For example, to increase the frequency of the data clock to improve the latency of restore operations, the local clock might need to be overclocked, which can, in turn, lead to increased power consumption.
Techniques are therefore needed to address the problems of implementing a hybrid memory module with a DRAM data clock having selectable frequencies that is synchronized with the data written to the DRAM during data restore operations. None of the aforementioned legacy approaches achieve the capabilities of the herein-disclosed techniques, therefore, there is a need for improvements.